Real-World Asynchronous Feedback Modeling
Supervisor: Dipl.-Inf. Gürkan Uygur
Vortragender: Florian Deeg
In the state of the art literature, a most common digital circuit system can be modeled as a mealy architecture. A Mealy is composed of two combinational structures, one for implementing the state transition function δ : (z,x) → δ(z,x) with state value z ∈ Z, another for implementing the output function λ : (z,x) → y. In case the output function μ only depends on z, μ : z → y, the model is described as Moore. And, if trivially feeding z, 1(z) = y with μ = 1 and 1 : z → 1(z), then the model is described as Medwedew. The sequential logic system becomes realized by asynchronously feeding the state value z back to the input z; this successfully works if δ is functionally stabilized, i.e. the following predicate logical expression holds: z = δ(z, x). At this point, it should be noticed, that using different symbols az and nz for old and new state values is somehow helpful for mathematically modeling sequential logic as combinational function, nevertheless in reality, the fully asynchronously feedback sequential structure determines the state value z by superimposing signals on the feedback.
Problem Definition: The problem definition is that asynchronously feed-backed circuitry is instantaneously underlying ana- logue principles. Therefore interfering signals can lead to hazardous glitches, metastabilities as well as races. In digital abstraction, such analog effects are undefined signals. Hence, generally spoken, a digital circuit system represents a partially defined function. Contrary to, in the state of the art modeling people mostly deploy a formalism and optimization approach that is based on a total and determined function, hard to derive from a given structure. The inconsistency between a formally derived (virtual) function and its underlying real-world structure is obvious.
Problem Solution: As an alternative solution to the problem definition above, instead of using don’t cares for modeling undefined inputs, we “implement partiality” by deploying a standardized sequential circuit structure (Moore). It doesn’t transmit the formally undefined inputs by “generating” a tristate behavior for incoming undefined signals. The analog effects triggered at this structural weakness can now — within digital abstraction — be interpreted as metastability and race, respectively. They are undefined values in digital view. For the uniquely encoding of partial logic we deploy the positive logic on positive as well as negative signals. These dual rails in addition with the RS-Buffer — provided with additional output for monitoring any violation of specified operation — warrants a function stable implementation of a partially defined logic.
Termin: 17.01.2017 10:15 Uhr